1. Field of the Invention
The present invention relates to semiconductor memory devices and a manufacturing method thereof, and more specifically to improvements and a manufacturing method of a high integrated structure of a semiconductor memory device, such as a dynamic random access memory (DRAM), having a memory cell structure including a field effect transistor and a capacitor.
2. Description of the Background Art
Recently, demand for a semiconductor memory device has been rapidly expanding with a remarkable spread of information equipments such as a computer. In addition, a large memory capacity and high speed operation are functionally requested. Under these circumstances, technology has been developed in respect to high integration and fast response or high reliability of a semiconductor memory device.
Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) is known which can randomly input/output information. A DRAM is generally comprises a memory cell array which is a storage region for storing a multiplicity of information, and peripheral circuitry required for communication between the storage region and outside.
FIG. 25 is a block diagram showing a general structure of a DRAM. Referring to FIG. 25, a DRAM includes a memory cell array 58, an address buffer 54, a row decoder 55 and a column decoder 56, and a sense amplifier 63. Memory array 58 includes a plurality of memory cells for storing a data signal of information. Address buffer 54 externally receives address signals A.sub.0 to A.sub.9 for selecting a memory cell constituting a unitary storage circuit. Row decoder 55 and column decoder 56 decode an address signal to designate the memory cell. Sense amplifier 63 is connected to memory array 58 for amplifying and reading a signal stored in the designated memory cell. An input buffer 59 and an output buffer 60 are connected through an I/O gate 57 to memory array 58. Input buffer 59 inputs a data signal. Output buffer 60 outputs a data signal. Address buffer 54 is connected so as to receive external address signals ext. A.sub.0 to A.sub.9 or internal address signals Q.sub.0 to Q.sub.8 generated from a refresh counter 53. A refresh controller 52 responds to a timing of a signal applied to a clock generator 51 to drive refresh counter 53. Clock generator 51 generates a clock signal which is a control signal to each section.
Memory array 58 occupying a large area on the semiconductor chip comprises a plurality of memory cells arranged in a matrix for storing unitary store information. FIG. 26 is a schematic diagram showing an equivalent circuit of four-bit memory cells constituting memory array 58. Memory array 58 comprises a plurality of word lines 301a, 301b, 301c, and 301d extending in parallel in a row direction, and a plurality of bit lines 302a and 302b extending in parallel in a column direction. Memory cells 303 are formed near intersections of word lines 301a to 301d and bit lines 302a and 302b. Each memory cell 303 comprises a MOS (metal oxide semiconductor) transistor 304 and a capacitor 305, which is a so-called one transistor-one capacitor type memory cell. A memory cell of this type facilitates, because of its simple structure, enhancement of integration of a memory array, and thus, is often employed in a DRAM of a large capacity. A pair of bit lines 302a and 302b shown in FIG. 26 arranged in parallel with sense amplifier 63 is referred to as a folded bit line type.
With reference to FIG. 26, MOS transistor 304 has its gate electrode connected to word line 301a, one source/drain electrode connected to one electrode of capacitor 305, and the other source/drain electrode connected to bit line 302a. In writing data, a prescribed voltage is applied to word line 301a, rendering MOS transistor 304 conductive, so that charges applied to bit line 302a are stored in capacitor 305. In reading data, a prescribed voltage is applied to word line 301a, rendering MOS transistor 304 conductive, so that charges stored in capacitor 305 are withdrawn through bit line 302a.
FIG. 27 shows an example of a partial planar arrangement of the DRAM shown in the equivalent circuit of FIG. 26. In FIG. 27, four memory cells are shown, each memory cell comprising one of MOS transistors Q1, Q2, Q3, and Q4 and one of capacitors Cs1, Cs2, Cs3, and Cs4, formed in one of operation areas A1, A2, A3, and A4, respectively. A gate electrode constituting each of transistors Q1-A4 comprises a part of one of word lines 301a to 301d corresponding to each memory cell. Over word lines 301a-301d, bit lines 302a and 302b are so formed as to be insulated from and cross word lines 301a-301d. Bit lines 302a and 302b are connected to the memory cell through contact holes C1, C2, and C3.
FIG. 28 is one example of a cross sectional view showing a structure of the memory cell taken along the 28--28 line in FIG. 27. FIG. 28 shows two-bit memory cells 303. Memory cell 303 comprises one MOS transistor 304 and one capacitor 305. MOS transistor 304 comprises a pair of source/drain regions 306a and 306b formed spaced apart from each other in a silicon substrate 340, and a gate electrode 308 (301b, 301c) formed on the surface of silicon substrate 340 with a gate oxide film 307 interposed therebetween. Capacitor 305 comprises a lower electrode (storage node) 309 connected to one of source/drain regions 306a of MOS transistor 304, a dielectric layer 310 formed on the upper surface of lower electrode 309, and an upper electrode (cell plate) 311 covering the upper surface of the electric layer 310. Lower electrode 309 and upper electrode 311 are made of polysilicon, for example. A capacitor of this stacked structure is referred to as a stacked capacitor. Stacked capacitor 305 has one end extended onto the upper portion of gate electrode 308 with an insulating film 312 interposed therebetween, and the other end extended onto the upper portion of a field oxide film 313. The surface of silicon substrate 340 on which capacitor 305 and the like are formed is covered with a thick interlayer insulating film 314. Bit line 302b formed on interlayer insulating film 314 is connected to the other of source/drain regions 306b of MOS transistor 304 through a contact hole 315.
In the memory cell structure of the DRAM shown in FIGS. 27 and 28, one contact hole 315 is formed for two memory cells 303, 303 (two bits). That is, one bit line contact is formed for two bits. Therefore, as high integration and miniaturization of the memory cell structure of the DRAM progress, contact hole 315 must be made smaller as possible. This leads to increase of contact resistance. Further, with the contact hole being smaller, an interconnection material to the contact portion can not be sufficiently buried, which leads to reduction of reliability. Additionally, as high integration and miniaturization of the memory cell structure of the DRAM progress, a space between bit lines becomes narrower, which makes very difficult to process the bit lines.